The present invention relates to a duty cycle correction circuit and a delay locked loop circuit including the same, and more particularly to a delay locked loop circuit capable of reducing the area and power consumption of the circuit.
Generally, delay locked loop circuits refer to circuits which control the timing of data output from a memory device using a clock input from outside of the memory device, e.g., a synchronous semiconductor memory device.
In order to transmit output data from the memory device to a chip set without an error, the memory device and the chip set should be synchronized with the clock. However, because the internal circuit of the memory device delays the clock input from the chip set to the memory device, a phase difference occurs between an external clock input to the memory device and an internal clock of the memory device. The delay locked loop circuit compensates the phase difference between the external clock and the internal clock by removing a clock skew caused by the memory device's internal circuit.
Meanwhile, it is very important accurately to control the duty cycle ratio of the clock used in the memory device. The duty cycle ratio is the ratio of an interval occupied by a high level section and an interval occupied by a low level section during one clock cycle. For example, if the duty cycle ratio is 50:50, it means that the high level section occupies a time interval equal to that of the low level section during one clock cycle.
When the duty cycle ratio of the clock is not accurately controlled, the margin of data is not secured, so that the data may be distorted. Especially, because the data is input or output not only at the rising edge but also at the falling edge of the clock in Double Data Rate (DDR) synchronous semiconductor memory devices (SDRAM), the duty cycle ratio of the clock is more important in relation to the margin security of the data section in the DDR SDRAM. The duty cycle correction circuit corrects the duty cycle ratio of the clock to 50:50.
FIG. 1 is block diagram of a delay locked loop circuit including a conventional duty cycle correction circuit. Referring to FIG. 1, the conventional delay locked loop circuit includes a first delay locked loop unit 101, a second delay locked loop unit 131, and a duty cycle correction unit 151.
The first delay locked loop unit 101 includes a first phase comparator 103, a first delayer 105 and a first replica model 107. The second delay locked loop unit 131 includes a second phase comparator 133, a second delayer 135 and a second replica model 137. The duty cycle correction unit 151 includes a phase mixer 153 and a duty cycle ratio detector 155.
The first phase comparator 103 compares phases of an external clock EXT_CLK and a first feedback clock FB_1 output from the first replica model 107. The first replica model 107 includes a clock delay component in a semiconductor memory device, and outputs the first feedback clock FB_1 by receiving a first internal clock CLK_1. The phase comparison result CMP_1 is input to the first delayer 105. The first delayer 105 delays the external clock EXT_CLK by controlling the delay degree to match the phase of the first feedback clock FB_1 with that of the external clock EXT_CLK, thereby outputting the first internal clock CLK_1 which is delay-fixed.
The second delay locked loop unit 131 performs an operation similar to the first delay locked loop unit 101 to match a phase of a second feedback clock FB_2 with that of the external clock EXT_CLK, and outputs a second internal clock CLK_2 which is delay-fixed. The rising edges of the second internal clock CLK_2 and the first internal clock CLK_1 are phase-matched with each other. However, because the second delayer 135 reverses the external clock EXT_CLK, the duty cycle ratio of the second internal clock CLK_2 is opposite to the duty cycle ratio of the first internal clock CLK_1. A bubble on the output terminal of the second delayer 135 means the reversal of the phase. For example, if the duty cycle ratio of the first internal clock CLK_1 is 40:60, the duty cycle ratio of the second internal clock CLK_2 is 60:40.
The first internal clock CLK_1 and the second internal clock CLK_2 are input to the duty cycle correction unit 151. The duty cycle ratio detector 155 detects the duty cycle ratios of the first internal clock CLK_1 and the second internal clock CLK_2 to output a correction signal CRTL to the phase mixer 153.
The phase mixer 153 corrects the duty cycle ratios of the first internal clock CLK_1 and the second internal clock CLK_2 in response to the correction signal CRTL. The phase mixer 153 drives the first internal clock CLK_1 and the second internal clock CLK_2 with a driving force varied in accordance with the duty cycle ratios of the first internal clock CLK_1 and the second internal clock CLK_2, and mixes the phases of the first internal clock CLK_1 and the second internal clock CLK_2.
The phase mixer 153 may include a plurality of inverters, which are turned on or off in response to the correction signal CRTL to drive the first internal clock CLK_1 and the second internal clock CLK_2 with different driving forces, respectively. The more inverters that are turned on in response to the correction signal CRTL, the more strongly the first internal clock CLK_1 or the second internal clock CLK_2 is driven.
FIG. 2 is a diagram illustrating an operation of the phase mixer 153 in FIG. 1, which shows a high level section of the first internal clock CLK_1 and the second internal clock CLK_2.
The high level section of the first internal clock CLK_1 as described with reference to FIG. 2 is narrower than a low level section of the first internal clock CLK_1.
The phase mixer 153 drives the first internal clock CLK_1 and the second internal clock CLK_2 by controlling a driving force in response to the correction signal CRTL. When the second internal clock CLK_2 be driven more strongly than the first internal clock CLK_1, the falling edge of the output signal from the phase mixer 153 moves toward the falling edge side of the second internal clock CLK_2. When the first internal clock CLK_1 is driven more strongly than the second internal clock CLK_2, the falling edge of the output signal from the phase mixer 153 moves toward the falling edge side of the first internal clock CLK_1.
FIG. 3 is a timing diagram of the clock of the delay locked loop circuit in FIG. 1.
The duty cycle ratio of the external clock EXT_CLK is not 50:50. The high level section is narrower than the low level section. The first internal clock CLK_1 is generated by delaying the external clock EXT_CLK by a delay degree in response to a phase comparison result CMP_1 of the first phase comparator 103. Similarly, the second internal clock CLK_2 is generated by delaying the external clock EXT_CLK by a delay degree in response to a phase comparison result CMP_2 of the second phase comparator 133. The rising edge of the second internal clock CLK_2 phase-matches the rising edge of the first internal clock CLK_1, but the duty cycle ratio is the opposite.
Because the duty cycle ratio of the first internal clock CLK_1 is opposite to that of the second internal clock CLK_2, the duty cycle ratio detector 155 outputs the correction signal CRTL turning on inverters so that the number of inverters driving the first internal clock CLK_1 may be identical to the number of inverters driving the second internal clock CLK_2. The phase mixer 153 mixed phases of the first internal clock CLK_1 and the second internal clock CLK_2 by driving the first internal clock CLK_1 and the second internal clock CLK_2 using the turned-on inverters. Accordingly, each of duty cycle ratios of the output clocks OUT_1 and OUT_2 becomes 50:50.
As described above, because the conventional delay locked loop circuit corrects the duty cycle ratio by generating two clocks, two delay locked loop units are provided. Accordingly, the conventional delay locked loop circuit requires a greater circuit area, and consumes much power.